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gs8182q18/36d-200/167/133 18mb burst of 2 sigmaquad-ii sram 200mhz?133mhz 1.8 v v dd 1.8 v and 1.5 v i/o 165-bump bga commercial temp industrial temp rev: 1.05c 2/2007 1/30 ? 2003, gsi technology specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. features ? simultaneous read and write sigmaquad? interface ? jedec-standard pinout and package ? dual double data rate interface ? byte write controls sampled at data-in time ? burst of 2 read and write ? 1.8 v +100/?100 mv core power supply ? 1.5 v or 1.8 v hstl interface ? pipelined read operation ? fully coherent read and write pipelines ? zq mode pin for programmable output drive strength ? ieee 1149.1 jtag-compliant boundary scan ? 165-bump, 13 mm x 15 mm, 1 mm bump pitch bga package ? pin-compatible with future 36mb, 72mb, and 144mb devices ? rohs-compliant 165-bump bga package available sigmaram ? family overview gs8182q18 are built in compliance with the sigmaquad-ii sram pinout standard for separate i/o synchronous srams. they are 18,874,368-bit (18mb) sr ams. these are the first in a family of wide, very low voltage hstl i/o srams designed to operate at the speeds needed to implement economical high performance networking systems. clocking and addressing schemes a burst of 2 sigmaquad-ii sram is a synchronous device. it employs two input register clock inputs, k and k . k and k are independent single-ended clock inputs, not differential inputs to a single differential clock input buffer. the device also allows the user to manipulate the output register clock inputs quasi independently with the c and c clock inputs. c and c are also independent single-ended clock inputs, not differential inputs. if the c clocks are tied high, the k clocks are routed internally to fire the output registers instead. because separate i/o burst of 2 rams always transfer data in two packets, a0 is internally set to 0 for the first read or write transfer, and automatically in cremented by 1 for the next transfer. because the lsb is tie d off internally, the address field of a burst of 2 ram is always one address pin less than the advertised index depth (e.g., the 1m x 18 has a 512k addressable index). parameter synopsis -200 -167 -133 tkhkh 5.0 ns 6.0 ns 7.5 ns tkhqv 0.45 ns 0.5 ns 0.5 ns 165-bump, 13 mm x 15 mm bga 1 mm bump pitch, 11 x 15 bump array bottom view jedec std. mo-216, variation cab-1 n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
1m x 18 sigmaquad-ii sr am ? top view (package d) 1 2 3 4 5 6 7 8 9 10 11 a cq mcl/sa (144mb) nc/sa (36mb) w bw1 k nc r sa mcl/sa (72mb) cq b nc q9 d9 sa nc k bw0 sa nc nc q8 c nc nc d10 v ss sa sa sa v ss nc q7 d8 d nc d11 q10 v ss v ss v ss v ss v ss nc nc d7 e nc nc q11 v ddq v ss v ss v ss v ddq nc d6 q6 f nc q12 d12 v ddq v dd v ss v dd v ddq nc nc q5 g nc d13 q13 v ddq v dd v ss v dd v ddq nc nc d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j nc nc d14 v ddq v dd v ss v dd v ddq nc q4 d4 k nc nc q14 v ddq v dd v ss v dd v ddq nc d3 q3 l nc q15 d15 v ddq v ss v ss v ss v ddq nc nc q2 m nc nc d16 v ss v ss v ss v ss v ss nc q1 d2 n nc d17 q16 v ss sa sa sa v ss nc nc d1 p nc nc q17 sa sa c sa sa nc d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. expansion addresses: a3 for 36mb, a10 for 72mb, a2 for 144mb 2. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 3. mcl = must connect low gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 2/30 ? 2003, gsi technology n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
512k x 36 sigmaquad sram ?top view (package d) 1 2 3 4 5 6 7 8 9 10 11 a nc mcl/sa (288mb) nc/sa (72mb) w bw2 k bw1 r nc/sa (36mb) mcl/sa (144mb) nc b q27 q18 d18 sa bw3 k bw0 sa d17 q17 q8 c d27 q28 d19 v ss sa sa sa v ss d16 q7 d8 d d28 d20 q19 v ss v ss v ss v ss v ss q16 d15 d7 e q29 d29 q20 v ddq v ss v ss v ss v ddq q15 d6 q6 f q30 q21 d21 v ddq v dd v ss v dd v ddq d14 q14 q5 g d30 d22 q22 v ddq v dd v ss v dd v ddq q13 d13 d5 h doff v ref v ddq v ddq v dd v ss v dd v ddq v ddq v ref zq j d31 q31 d23 v ddq v dd v ss v dd v ddq d12 q4 d4 k q32 d32 q23 v ddq v dd v ss v dd v ddq q12 d3 q3 l q33 q24 d24 v ddq v ss v ss v ss v ddq d11 q11 q2 m d33 q34 d25 v ss v ss v ss v ss v ss d10 q1 d2 n d34 d26 q25 v ss sa sa sa v ss q10 d9 d1 p q35 d35 q26 sa sa c sa sa q9 d0 q0 r tdo tck sa sa sa c sa sa sa tms tdi 11 x 15 bump bga?13 x 15 mm 2 body?1 mm bump pitch notes: 1. expansion addresses: a9 for 36mb, a3 for 72mb, a10 for 144mb, a2 for 288mb 2. bw0 controls writes to d0:d8. bw1 controls writes to d9:d17. 3. bw2 controls writes to d18:d26. bw3 controls writes to d27:d35. 4. mcl = must connect low 5. it is recommended that h1 be tied low for compatibility with future devices. gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 3/30 ? 2003, gsi technology n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
pin description table symbol description type comments sa synchronous address inputs input ? nc no connect ? ? r synchronous read input active low w synchronous write input active low bw0 ? bw1 synchronous byte writes input active low k input clock input active high k input clock input active low c output clock input active high c output clock input active low tms test mode select input ? tdi test data input input ? tck test clock input input ? tdo test data output output ? v ref hstl input reference voltage input ? zq output impedance matching input input ? mcl must connect low ? ? d0?d17 synchronous data inputs input ? q0?q17 synchronous data outputs output ? doff disable dll when low input active low cq output echo clock output ? cq output echo clock output ? v dd power supply supply 1.8 v nominal v ddq isolated output buffer supply supply 1.8 or 1.5 v nominal v ss power supply: ground supply ? gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 4/30 ? 2003, gsi technology note: nc = not connected to die or any other pin n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 5/30 ? 2003, gsi technology background separate i/o srams, from a syst em architecture point of view, are attractive in applications where alte rnating reads and writes are needed. therefore, the sigmaquad- ii sram interface and truth table are optimized for alternating reads a nd writes. separate i/o srams are unpopular in app lications where multiple reads or multiple writes are needed because burst read or write transfers fr om separate i/o srams can cut the ram?s bandwidth in half. a sigmaquad-ii sram can begin an alternat i ng sequence of reads and writ es with either a read or a write. in order for any separate i/o sram that shares a common address between its tw o ports to keep both ports running all the time, the ram must implement some sort of burst transfer protocol. the burst must be at least long enough to cover the time the opposite port is receiving instructions on what to do ne xt. the rate at which a ram can accept a new random address is th e most fundamental performance metric for the ram. each of the three sigmaquad- ii srams support similar address rates because random address rate is determined by the internal perfor mance of the ram and they are all based on the same internal circuits. differences between the truth tables of the different si gmaquad-ii srams, or any other separate i/o srams, follow from differences in how the ram?s interface is contrived to interact with the rest of the system. each mode of operation has its own advantages and disadvantages. the user should cons ider the nature of the work to be done by the ram to evaluate which version is best suited t o the application at hand. alternating read-write operations sigmaquad-ii srams follow a few simple rules of operation. - read or write commands issued on one po rt are never allowed to interrupt an operation in progress on the other port. - read or write data transfers in progres s may not be interrupted and re-started. - r and w high always deselects the ram. - all address, data, and control inp u ts are sampled on clock edges. in order to enforce these rules, each ram combines present st ate information with command i nputs. see the truth table for details. n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 6/30 ? 2003, gsi technology sigmaquad-ii b2 sram ddr read the read port samples the stat us of th e ad dress input and r pins at each rising edge of k. a low on the read enable-bar pin, r , begins a read cycle. data can be clocked out after the next rising edge of k with a rising edge of c (or by k if c and c are tied high), and after the following rising edge of k with a rising edge of c (or by k if c and c are tied high). clocking in a high on the read enable-bar pin, r , begins a read port deselect cycle. burst of 2 double data rate sigmaquad-ii sram read first read a nop write b read c write d read e write f read g write h a b c d e f g h b b+1 d d+1 f f+1 h h+1 b b+1 d d+1 f f+1 h h+1 a a+1 c c+1 e k k address r w bwx d c c q cq cq n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 7/30 ? 2003, gsi technology burst of 2 sigmaquad-ii sram ddr write the write port samples the status of the w pin at each rising edge of k and the address input pins on the following rising edge of k . a low on the write enable-bar pin, w , begins a write cycle. the firs t of the data-in pairs associat ed with the write command is clocked in with the same rising edge of k used to capture the wr ite command. the second of the tw o data in transfers is capture d on the rising edge of k along with the write address. a high on w causes a write port deselect cycle. burst of 2 double data rate sigmaquad-ii sram write first write a read b read c write d nop read e write f read g write h nop a b c d e f g h a a+1 d d+1 f f+1 h h+1 a a+1 d d+1 f f+1 h h+1 b b+1 c c+1 e e+1 k k address r w bwx d c c q cq cq special functions byte write control byte write enable pins are sampled at the same time that data in is sam pl ed. a high on the byte write enable pin associated wit h a particular byte (e.g., bw0 controls d0?d8 inputs) will inhibit the storage of that particular byte, leaving whatever data may be stored at the current address at that byte location undisturbed. a ny or all of the byte write enable pins may be driven high or low during the data in sample times in a write sequence. each write enable command and write addres s loaded into the ram provides the base ad dress for a 2 beat data transfer. the x18 version of the ram, for example, may write 36 bits in associatio n with each address loaded. any 9-bit byte may be masked in any write sequence. n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
example x18 ram write sequence using byte write enables data in sample tim e bw0 bw1 d0?d8 d9?d17 beat 1 0 1 data in don?t care beat 2 1 0 don?t care data in resulting write operation byte 1 d0?d8 byte 2 d9?d17 byte 3 d0?d8 byte 4 d9?d17 written unchanged unchanged written gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 8/30 ? 2003, gsi technology output register control sigmaquad-ii srams offer two mechanisms for controlling the output d a ta registers. typically, control is handled by the output register clock inputs, c and c . the output register clock inputs can be used to make small phase adjustments in the firing of the output registers by allowing the user to delay driving data out as much as a few nanoseconds beyond the next rising edges of th e k and k clocks. if the c and c clock inputs are tied high, the ram reverts to k and k control of the outputs, allowing the ram to function as a conventional pipelined read sram. n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
a k r w a 0 ?a n k w 0 d 1 ?d n bank 0 bank 1 bank 2 bank 3 r 0 d a k w d a k w d a k w d r r r qqq q cc cc q 1 ?q n c w 1 r 1 w 2 r 2 w 3 r 3 note: for simplicity bwn , nwn , k , and c are not shown. cq cq cq cq cq 0 cq 1 cq 2 cq 3 gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 9/30 ? 2003, gsi technology example four bank dept h expansion schematic n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 10/30 ? 2003, gsi technology burst of 2 sigmaquad-ii sram depth expansion read a write b read c write d read e write f read g write h read i write j read k write l nop a b c d e f g h i j k l f f+1 h h+1 j j+1 f f+1 h h+1 j j+1 b b+1 d d+1 l l+1 b b+1 d d+1 l l+1 a a+1 g g+1 i i+1 c c+1 e e+1 k k address r (bank1) r (bank2) w (bank1) w (bank2) bwx (bank1) d(bank1) bwx (bank2) d(bank2) c(bank1) c (bank1) q(bank1) cq(bank1) cq (bank1) c(bank2) c (bank2) q(bank2) cq(bank2) cq (bank2) n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 11/30 ? 2003, gsi technology flxdrive-ii output driver impedance control hstl i/o sigmaquad-ii srams are supplied wi th programm able impedance output drivers. the zq pin must be connected to v ss via an external resistor, rq, to allow th e sram to monitor and adjust its output driver impedance. the value of rq must be 5x the value of the intended line impedance driven by the sram. the allowable range of rq to guarantee impedance matching with a vendor-specified tolerance is between 150 ? and 300 ? . periodic readjustment of the output driver impedance is necessary as the impedance is affected by drifts in supply voltage and te mperature. the sram?s output impe dance circuitry compensates for drifts in supply voltage and temperature ev ery 1024 cycles. a clock cycle counter peri odically triggers an impedance evaluatio n, resets and counts again. each impedance evaluation may move the output driver impedance level on e step at a time towards the optimum level. the output driver is implemented with discrete binary weighted impedance steps. burst of 2 coherency an d pass through functions because the burst of 2 read and write commands are loaded at the same time, there may be some confusion over what constitutes ?coherent? operation. normally, one would expect a ram to produ ce the just-written data when it is read immediately after a write. this is true of the burst of 2 except in one case, as is illustrated in the following diagram. if the user holds the sam e address value in a given k clock cycle, loading the same address as a r ead address and then as a matchi ng write address, the burst of 2 will read or ?pass-thru? the latest data input, rather than the data from the previously completed write operation. dwg rev. g db0 db1 dd0 dd1 df0 df1 dh0 dh1 di0 qa0 qa1 qc0 qc1 qe0 qe1 71 write read oo io 56 oi 3 write read write c /r /w /bwx read write address oo oi oi oo oo oo read k /k d q ?? 5 /c 4 682719 hi abcdefg coherent pass-thru burst of 2 coherency and pass through functions n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
separate i/o burst of 2 sigmaq uad-ii sram read truth table a r output next state q q k (t n ) k (t n ) k (t n ) k (t n+1 ) k (t n+1? ) x 1 deselect hi-z hi-z v 0 read q0 q1 notes: 1. x = don?t care, 1 = high, 0 = low, v = valid. 2. r is evaluated on the rising edge of k. 3. q0 and q1 are the first and second data output transfers in a read. separate i/o burst of 2 sigmaq uad-ii sram write truth table a w bwn bwn input next state d d k (t n + ? ) k (t n ) k (t n ) k (t n + ? ) k , k (tn), (tn + ?) k (t n ) k (t n + ? ) v 0 0 0 write byte dx0, write byte dx1 d0 d1 v 0 0 1 write byte dx0, write abort byte dx1 d0 x v 0 1 0 write abort byte dx0, write byte dx1 x d1 x 0 1 1 write abort byte dx0, write abort byte dx1 x x x 1 x x deselect x x notes: 1. x = don?t care, h = high, l = low, v = valid. 2. w is evaluated on the rising edge of k. 3. d0 and d1 are the first and second data input transfers in a write. 4. bwn represents any of the byte write enable inputs ( bw0 , bw1 , etc.). x18 byte write enable ( bwn ) truth table bw0 bw1 d0?d8 d9?d17 1 1 don?t care don?t care 0 1 data in don?t care 1 0 don?t care data in 0 0 data in data in gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 12/30 ? 2003, gsi technology n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 13/30 ? 2003, gsi technology state diagram power-up read nop load new read address ddr read write nop load new write address ddr write write read read write read write always (fixed) always (fixed) read write notes: 1. internal burst counter is fixed as 1-bit linear (i.e., when first address is a0 +), next internal burst address is a0+1. 2. ?read? refers to read active status with r = low, ?read ? refers to read inactive status with r = high. the same is true for ?write? and ?write ?. 3. read and write state machine can be active simultaneously. 4. state machine control timing sequence is controlled by k. n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
absolute maximum ratings (all voltages reference to v ss ) symbol description value unit v dd voltage on v dd pins ?0.5 to 2.9 v v ddq voltage in v ddq pins ?0.5 to v dd v v ref voltage in v ref pins ?0.5 to v ddq v v i/o voltage on i/o pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v v in voltage on other input pins ?0.5 to v ddq +0.5 ( 2.9 v max.) v i in input current on any pin +/?100 ma dc i out output current on any i/o pin +/?100 ma dc t j maximum junction temperature 125 o c t stg storage temperature ?55 to 125 o c t sub storage under bias ?50 to 100 o c note: permanent damage to the device may occur if the absolute maximu m ratings are exceeded. operati on should be restricted to recomm ended operating conditions. exposure to conditi ons exceeding the recommended operating condi tions, for an extended period of time, ma y affect reliability of this component. gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 14/30 ? 2003, gsi technology recommended oper ating conditions power supplies parameter symbol min. typ. max. unit notes supply voltage v dd 1.7 1.8 1.95 v 1.5 v i/o supply voltage v ddq 1.4 1.5 1.65 v 1 1.8 v i/o supply voltage v ddq 1.7 1.8 1.95 v 1 reference voltage v ref 0.68 ? 0.95 v 1 notes: 1. unless otherwise noted, all perfo rmance sp ecifications quoted are eva luated for worst case at both 1.4 v v ddq 1.6 v (i.e., 1.5 v i/o) and 1.7 v v ddq 1.95 v (i.e., 1.8 v i/o) and quoted at whichever condition is worst case. 2. the power supplies need to be powered up simu ltane ously or in the following seq uence: v dd , v ddq , v ref , followed by signal inputs. the power down sequence must be the reverse. v ddq must not exceed v dd . operating temperature parameter symbol min. typ. max. unit ambient temperature (commercial range versions) t a 0 25 70 c ambient temperature (industrial range versions) t a ?40 25 85 c n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 15/30 ? 2003, gsi technology hstl i/o dc input characteristics parameter symbol min max units notes dc input logic high v ih (dc) v ref + 200 mv ? dc input logic low v il (dc) v ref ? 200 mv ? v ref dc voltage v ref (dc) v ddq (min)/2 v ddq (max)/2 v ? note: compatible with both 1.8 v and 1.5 v i/o drivers hstl i/o ac input characteristics parameter symbol min max units notes ac input logic high v ih (ac) v ref + 400 mv 3,4 ac input logic low v il (ac) v ref ? 400 mv 3,4 v ref peak to peak ac voltage v ref (ac) 5% v ref (dc) mv 1 notes: 1. the peak to peak ac component superimposed on v ref may not exceed 5% of the dc component of v ref . 2. to guarantee ac characteristics, v ih ,v il , trise, and tfall of inputs and clocks must be within 10% of each other. 3. for devices supplied with hstl i/o input buffers . compatible with both 1.8 v and 1.5 v i/o drivers. 4. see ac input definition drawing below. v ih (ac) v ref v il (ac) hstl i/o ac input definitions 20% tkhkh v ss ? 1.0 v 50% v ss v ih undershoot measurement and timing overshoot measure ment and timing 20% tkhkh v dd + 1.0 v 50% v dd v il n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
capacitance o c, f = 1 mh z , v dd parameter symbol test conditions typ. max. unit input capacitance c in v in = 0 v 4 5 pf output capacitance c out v out = 0 v 6 7 pf note: this parameter is sample tested. gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 16/30 ? 2003, gsi technology ac test conditions parameter conditions input high level v ddq input low level 0 v max. input slew rate 2 v/ns input reference level v ddq /2 output reference level v ddq /2 notes: test conditions as specified with output loading as shown unless otherwise noted. dq vt = v ddq /2 50? rq = 250 ? (hstl i/o) v ref = 0.75 v ac test load diagram input and output leakage characteristics parameter symbol test conditions min. max notes input leakage current (except mode pins) i il v in = 0 to v dd ?2 ua 2 ua output leakage current i ol output disable, v out = 0 to v ddq ?2 ua 2 ua (t a = 25 = 3.3 v) n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 17/30 ? 2003, gsi technology programmable impedance hstl output driver dc electrical characteristics parameter symbol min. max. units notes output high voltage v oh1 v ddq /2 v ddq v 1, 3 output low voltage v ol1 vss v ddq /2 v 2, 3 output high voltage v oh2 v ddq ? 0.2 v ddq v 4, 5 output low voltage v ol2 vss 0.2 v 4, 6 notes: 1. i oh = (v ddq /2) / (rq/5) +/? 15% @ v oh = v ddq /2 (for: 175? rq 350 ?). 2. i ol = (v ddq /2) / (rq/5) +/? 15% @ v ol = v ddq /2 (for: 175 ? rq 350?) . 3. parameter tested with rq = 250 ? and v ddq = 1.5 v or 1.8 v 4. minimum impedance mode, zq = v ss 5. i oh = ?1.0 ma 6. i ol = 1.0 ma operating currents parameter org symbol -200 -167 -133 test conditions 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c 0c to 70c ?40c to +85c operating current x18 idd 520 ma 530 ma 455 ma 465 ma 385 ma 395 ma v dd =max.; i out = 0 ma; cycle time t khkh min. x36 675 ma 685 ma 585 ma 595 ma 500 ma 510 ma standby current (nop) x18 isb1 200 ma 205 ma 190 ma 195 ma 170 ma 175 ma device deselected; i out = 0 ma; f = max; all inputs 0.2 v or v dd ? 0.2 v x36 255 ma 260 ma 240 ma 245 ma 220 ma 225 ma notes: 1. power measured with output pins floating. 2. all inputs (except zq, v ref ) are held at either v ih or v il . 3. operating supply currents are measured at 100% buss utilization. 4. nop currents are valid when entering nop after all pending re ad and write cycles are completed. n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 18/30 ? 2003, gsi technology ac electrical characteristics parameter symbol -200 -167 -133 units notes min max min max min max clock k, k clock cycle time c, c clock cycle time t khkh t chch 5.0 7.88 6.0 7.88 7.5 8.4 ns tkc variable t kcvar ? 0.2 ? 0.2 ? 0.2 ns 5 k, k clock high pulse width c, c clock high pulse width t khkl t chcl 2.0 ? 2.4 ? 3.0 ? ns k, k clock low pulse width c, c clock low pulse width t klkh t clch 2.0 ? 2.4 ? 3.0 ? ns k to k high c to c high t kh kh 2.3 ? 2.8 ? 3.2 ? ns k, k clock high to c, c clock high t khch 0 2.3 0 2.8 0 3.5 ns dll lock time t kclock 1024 ? 1024 ? 1024 ? cycle 6 k static to dll reset t kcreset 30 ? 30 ? 30 ? ns output times k, k clock high to data output valid c, c clock high to data output valid t khqv t chqv ? 0.45 ? 0.5 ? 0.5 ns 3 k, k clock high to data output hold c, c clock high to data output hold t khqx t chqx ?0.45 ? ?0.5 ? ?0.5 ? ns 3 k, k clock high to echo clock valid c, c clock high to echo clock valid t khcqv t chcqv ? 0.45 ? 0.5 ? 0.5 ns k, k clock high to echo clock hold c, c clock high to echo clock hold t khcqx t chcqx ?0.45 ? ?0.5 ? ?0.5 ? ns cq, cq high output valid t cqhqv ? 0.35 ? 0.40 ? 0.40 ns 7 cq, cq high output hold t cqhqx ?0.35 ? ?0.40 ? ?0.40 ? ns 7 k clock high to data output high-z c clock high to data output high-z t khqz t chqz ? 0.45 ? 0.5 ? 0.5 ns 3 k clock high to data output low-z c clock high to data output low-z t khqx1 t chqx1 ?0.45 ? ?0.5 ? ?0.5 ? ns 3 setup times address input setup time t avkh 0.4 ? 0.5 ? 0.5 ? ns control input setup time t ivkh 0.4 ? 0.5 ? 0.5 ? ns 2 data input setup time t dvkh 0.4 ? 0.5 ? 0.5 ? ns n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 19/30 ? 2003, gsi technology hold times address input hold time t khax 0.4 ? 0.5 ? 0.5 ? ns control input hold time t khix 0.4 ? 0.5 ? 0.5 ? ns data input hold time t khdx 0.4 ? 0.5 ? 0.5 ? ns notes: 1. all address inputs must meet the specified setup and hold times for all latching clock edges. 2. control singles are r , w , bw0 , bw1 , and ( nw0 , nw1 for x8) and ( bw2 , bw3 for x36). 3. if c, c are tied high, k, k become the references for c, c timing parameters 4. to avoid bus contention, at a given volt age and temperature tchqx1 is bigger than tchq z. the specs as shown do not imply bu s contention because tchqx1 is a min parameter that is worst case at totally different test conditions (0 c, 1.9 v) than tchqz, which is a max parameter (worst case at 70 c, 1.7 v). it is not possible for two srams on the same board to be at such different voltages and temperatures. 5. clock phase jitter is the variance from cloc k rising edge to the next expected clock rising edge. 6. v dd slew rate must be less than 0.1 v dc per 50 ns for dll lock retention. dll lock time begins once v dd and input clock are stable. 7. echo clock is very tightly controlled to data valid/data hold. by design, there is a 0.1 ns variation from echo clock to da ta. the datasheet para meters reflect tester guard bands and test setup variations. ac electrical character istics (continued) parameter symbol -200 -167 -133 units notes min max min max min max n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 20/30 ? 2003, gsi technology k and k controlled read-wr ite-read timing diagram read a write b nop read c read d write e write f read g write h nop a b c d e f g h b b+1 e e+1 f f+1 h h+1 a a+1 c c+1 d d+1 g khqz khqv cqhqv khqx cqhqx khqx1 khcqv khcqx khcqv khcqx khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh khkhbar klkhklkh khklkhkl khkhkhkh k k address r w bwx d cq cq q n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 21/30 ? 2003, gsi technology c and c controlled read-wr ite-read timing diagram read a write b nop write c read d write e read f write g read h nop a b c d e f g h b b+1 c c+1 e e+1 g g+1 a a+1 d d+1 f f+1 h chcqv chcqx cqhqv cqhqx chcqv chcqx chqx chqv chqz chqx1 khkhbar klkhklkh khklkhkl khkhkhkh khdx dvkh khix ivkh khix ivkh khix ivkh khax avkh khkhbar klkhklkh khklkhkl khkhkhkh k k address r w bwx d c c q cq cq jtag port operation overview the jtag port on this ram operates in a manner that is compliant with ieee standard 1149.1-1990, a serial boundary scan interface standard (commonly referred to as jtag). the jtag port input inte rface levels scale with v dd . the jtag output drivers are powered by v ddq . n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 22/30 ? 2003, gsi technology disabling the jtag port it is possible to use this device without utilizing the jtag port. the port is reset at power-up and will remain inactive unles s clocked. tck, tdi, and tms are designed with internal pull-up circuits.to assure normal operation of the ram with the jtag port unused, tck, tdi, and tms may be left floating or tied to either v dd or v ss . tdo should be left unconnected. jtag pin descriptions pin pin name i/o description tck test clock in clocks all tap events. all i nputs are captured on the rising edge of tck and a ll outputs propagate from the falling edge of tck. tms test mode select in the tms input is sampled on the rising edge of tck. this is t he command input for the t ap controller state machine. an undriven tms input wi ll produce the same result as a logic one input level. tdi test data in in the tdi input is sampled on the rising edge of tck. this is the input side of the serial registers pla c ed between tdi and tdo. the register placed between tdi and tdo is determined by the state of the tap controller state machine and the instruction that is currently loaded in the tap instruction register (refer to the tap controll er state diagram). an undriven tdi pin will produce the same result as a logic one input level. tdo test data out out output that is active depending on the state o f the tap state machine. output changes in response to the falling edge of tck. this is the out put side of the serial registers placed between tdi and tdo. note: this device does not have a trst (tap reset) pin. trst is optional in ie ee 1149.1. the test-logic-reset state is entered while tms is held high for five rising edges of tck. the tap cont roller is also reset automaticly at power-up. jtag port registers overview the various jtag registers, refered to as tes t access port ortap registers, are select ed (one at a time) via the sequences of 1 s and 0s applied to tms as tck is strobed. each of the tap regist ers is a serial shift register that captures serial input data o n the rising edge of tck and pushes serial data out on the next falling edge of tck. when a register is selected, it is placed betwe en the tdi and tdo pins. instruction register the instruction register holds the instructi ons that are executed by the ta p controller when it is moved into the run, test/idl e, or the various data register states. instructions are 3 bits long. th e instruction register can be lo aded when it is placed betwee n the tdi and tdo pins. the instruction register is automatically preloa ded with the idcode instruction at power-up or whenever the controller is placed in test-logic-reset state. bypass register the bypass register is a single bit register that can be placed between tdi and tdo. it allows serial test data to be passed th rough the ram?s jtag port to another device in the scan chain with as little delay as possible. boundary scan register the boundary scan register is a collection of flip flops that can be preset by the logic level found on the ram?s input or i/o pin s . the flip flops are then daisy chained togeth er so the levels found can be shifted seri ally out of the jtag port?s tdo pin. the boundary scan register also includes a number of place holder flip fl ops (always set to a logic 1). the relationship between t he device pins and the bits in the boundary scan register is described in the scan order table following. the boundary scan register, under the control of the tap contro ller, is loaded with the contents of the rams i/o ring when the controller is in capture-dr state and then is placed between the tdi and tdo pins when the controller is moved to shift-dr state. sample-z, sample/preload and extest instructions can be us ed to activate the boundary scan register. n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
instruction register id code register boundary scan register 012 0 31 30 29 1 2 0 bypass register tdi tdo tms tck test access port (tap) controller 108 1 0 control signals gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 23/30 ? 2003, gsi technology jtag tap block diagram identification (id) register the id register is a 32-bit register that is loaded with a device and vendor specific 32-bit code when the controller is put in capture-dr state with the idcode command loaded in the instruction re gister. the code is loaded from a 32-bit on-chip rom. it describes various attributes of the ram as indicated below. the register is then placed between the tdi and tdo pins when th e controller is moved into shift- dr state. bit 0 in the register is the lsb and the first to reach tdo when shifting begins. id register contents not used gsi technology jedec vendor id code presence register bit # 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 x x x x x x x x x x x x x x x x x x x x 0 0 0 1 1 0 1 1 0 0 1 1 n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 24/30 ? 2003, gsi technology tap controller instruction set overview there are two classes of instructions defined in the standard 114 9.1-1 990; the standard (public) instructions, and device speci fic (private) instructions. some public instructions are mandatory for 1149.1 compliance. optional public instructions must be implemented in prescribed ways. the tap on th is device may be used to monitor all inpu t and i/o pads, and can be used to load address, data or control signals into the ram or to preload the i/o buffers. when the tap controller is placed in captur e-ir s t ate the two least significant bits of the instruction regi ster are loaded wit h 01. when the controller is moved to the shift-ir state the instruction register is placed between tdi and tdo. in this state the de sired instruction is serially loaded through the tdi input (while the previous contents are shifted out at tdo). for all instructions , the tap executes newly loaded instruct ions only when the controller is moved to update-ir state. the tap instruction set for this device is listed in the following table. select dr capture dr shift dr exit1 dr pause dr exit2 dr update dr select ir capture ir shift ir exit1 ir pause ir exit2 ir update ir test logic reset run test idle 0 0 1 0 1 1 0 0 1 1 1 0 0 1 1 0 0 0 0 1 1 0 0 1 10 0 0 1 11 1 jtag tap controller state diagram instruction descriptions bypass when the bypass instruction is loaded in the instruction register the bypass regi ster is placed between tdi and tdo. this occurs when the tap controller is moved to the shift-dr state. this allows the board level scan path to be shortened to facili - tate testing of other devices in the scan path. n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 25/30 ? 2003, gsi technology sample/preload sample/preload is a standard 1149.1 mandatory public in stru ction . when the sample / preload instruction is loaded in the instruction register, moving the tap controller into the capture-dr state loads the data in the rams input and i/o buffers into the boundary scan register. boundary scan regist er locations are not associated with an input or i/o pin, and are loaded with the default stat e identified in the boundary s can chain table at the end of th is section of the datasheet. beca use the ram clock is independent from the tap clock (tck) it is possible for the tap to attempt to capture the i/o ring contents while the input buffers are in transition (i.e. in a metastable state). although allowing the tap to sample metastable inputs w ill not harm the device, repeatable results cannot be expected. ram input signals must be stabilized for long enough to meet the taps input data capture set-up plus hold time (tts plus tth) . the rams clock inputs need not be paused for any other tap operation except capturing the i/o ring contents into the boundary s can register. moving the contro ller to shift-dr state then places the boundary scan register between the tdi and tdo pins. extest extest is an ieee 1149.1 mandatory public instruction. it is to be executed whenever the instru ction register is loaded with all logic 0s. the extest command does not block or override th e ram?s input pins; therefore, the ram?s internal state is still determined by its input pins. typically, the boundary scan re gister is loaded with the desired pattern of data with the sample/preload command. then the extest command is used to outp ut the boundary scan register?s contents, in parallel, on the ram?s data output drivers on the falling edge of tck when the controller is in the update-ir state. alternately, the boundary scan register ma y be loaded in parallel using the extest command. when the extest instruc - tion is selected, the sate of all the ram?s input and i/o pins, as well as the defau lt val ues at scan register locations not as so - ciated with a pin, are transfer red in parallel into the boundary scan regist er on the rising edge of tck in the capture-dr state, the ram?s output pins drive out the value of the boundar y scan register location with which each output pin is associ - ated. idcode the idcode instruction causes the id rom to be loaded into the id registe r when the controller is in capture-dr mode and places the id register between the tdi a nd tdo pins in shift-dr mode. the idcode instruction is the default instruction loaded in at power up and any time the controller is placed in the test-logic-reset state. sample-z if the sample-z instruction is loaded in the ins t ruction register, all ram outputs are forced to an inactiv e drive state (high- z) and the boundary scan register is connected between tdi and t do when the tap controller is moved to the shift-dr state. rfu these instructions are reserved fo r fu ture use. in this device they replicate the bypass instruction. jtag tap instruction set summary instruction code description notes extest 000 places the boundary scan re gister between tdi and tdo. 1 idcode 001 preloads id register and places it between tdi and tdo. 1, 2 sample-z 010 captures i/o ring contents. places the b oundary scan regis ter between tdi and tdo. forces all ram output drivers to high-z. 1 rfu 011 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 26/30 ? 2003, gsi technology jtag port recommended operating conditions and dc characteristics parameter symbol min. max. unit notes test port input low voltage v ilj ? 0.3 0.3 * v dd v 1 test port input high voltage v ihj 0.6 * v dd v dd +0.3 v 1 tms, tck and tdi input leakage current i inhj ? 300 1 ua 2 tms, tck and tdi input leakage current i inlj ? 1 100 ua 3 tdo output leakage current i olj ? 1 1 ua 4 test port output high voltage v ohj 1.7 ? v 5, 6 test port output low voltage v olj ? 0.4 v 5, 7 test port output cmos high v ohjc v ddq ? 100 mv ? v 5, 8 test port output cmos low v oljc ? 100 mv v 5, 9 notes: 1. input under/overshoot voltage must be ? 1 v < v i < v ddn +1 v not to exceed 2.9 v maximum, with a pulse width not to exceed 20% ttkc. 2. v ilj v in v ddn 3. 0 v v in v iljn 4. output disable, v out = 0 to v ddn 5. the tdo output driver is served by the v ddq supply. 6. i ohj = ? 4 ma 7. i olj = + 4 ma 8. i ohjc = ?100 ua 9. i oljc = +100 ua sample/ p r eload 100 captures i/o ring contents. places the b oundary scan regis ter between tdi and tdo. 1 gsi 101 gsi private instruction. 1 rfu 110 do not use this instruction; reserved for future use. replicates bypass instruction. places bypass register between tdi and tdo. 1 bypass 11 1 places bypass register between tdi and tdo. 1 notes: 1. instruction codes expressed in binary, msb on left, lsb on right. 2. default instruction automatically loaded at power-up and in test-logic-reset state. jtag tap instruction set summary n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
notes: 1. include scope and jig capacitance. 2. test conditions as shown unless otherwise noted. jtag port ac test conditions parameter conditions input high level v dd ? 0.2 v input low level 0.2 v input slew rate 1 v/ns input reference level v ddq /2 output reference level v ddq /2 dq v ddq /2 50? 30pf * jtag port ac test load * distributed test jig capacitance gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 27/30 ? 2003, gsi technology jtag port timing diagram tth tts ttkq tth tts tth tts ttklttkl ttkhttkh ttkcttkc tck tdi tms tdo parallel sram input jtag port ac electri cal characteristics parameter symbol min max unit tck cycle time ttkc 50 ? ns tck low to tdo valid ttkq ? 20 ns tck high pulse width ttkh 20 ? ns tck low pulse width ttkl 20 ? ns tdi & tms set up time tts 10 ? ns tdi & tms hold time tth 10 ? ns n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 28/30 ? 2003, gsi technology package dimensions?165-b ump fpbga (package d) a b c d e f g h j k l m n p r a b c d e f g h j k l m n p r 1 2 3 4 5 6 7 8 9 10 11 11 10 9 8 7 6 5 4 3 2 1 a1 corner top view a1 corner bottom view 1.0 1.0 10.0 1.0 1.0 14.0 130.05 150.05 a b 0.20(4x) ?0.10 ?0.25 c c a b m m ?0.40~0.60 (165x) c seating plane 0.20 c 0.36~0.46 1.40 max. n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
ordering information?gs i sigmaquad-ii sram org part number 1 type package speed (mhz) t a 2 status 3 1m x 18 gs8182q18d-200 sigmaquad-ii sram 165-pin bga 200 c mp 1m x 18 gs8182q18d-167 sigmaquad-ii sram 165-pin bga 167 c mp 1m x 18 gs8182q18d-133 sigmaquad-ii sram 165-pin bga 133 c mp 1m x 18 GS8182Q18D-200I sigmaquad-ii sram 165-pin bga 200 i mp 1m x 18 gs8182q18d-167i sigmaquad-ii sram 165-pin bga 167 i mp 1m x 18 gs8182q18d-133i sigmaquad-ii sram 165-pin bga 133 i mp 1m x 18 gs8182q18gd-200 sigmaquad-ii sram rohs-compliant 165-pin bga 200 c mp 1m x 18 gs8182q18gd-167 sigmaquad-ii sram rohs-compliant 165-pin bga 167 c mp 1m x 18 gs8182q18gd-133 sigmaquad-ii sram rohs-compliant 165-pin bga 133 c mp 1m x 18 gs8182q18gd-200i sigmaquad-ii sram rohs-compliant 165-pin bga 200 i mp 1m x 18 gs8182q18gd-167i sigmaquad-ii sram rohs-compliant 165-pin bga 167 i mp 1m x 18 gs8182q18gd-133i sigmaquad-ii sram rohs-compliant 165-pin bga 133 i mp 512k x 36 gs8182q36d-200 sigmaquad-ii sram 165-pin bga 200 c mp 512k x 36 gs8182q36d-167 sigmaquad-ii sram 165-pin bga 167 c mp 512k x 36 gs8182q36d-133 sigmaquad-ii sram 165-pin bga 133 c mp 512k x 36 gs8182q36d-200i sigmaquad-ii sram 165-pin bga 200 i mp 512k x 36 gs8182q36d-167i sigmaquad-ii sram 165-pin bga 167 i mp 512k x 36 gs8182q36d-133i sigmaquad-ii sram 165-pin bga 133 i mp 512k x 36 gs8182q36gd-200 sigmaquad-ii sram rohs-compliant 165-pin bga 200 c mp 512k x 36 gs8182q36gd-167 sigmaquad-ii sram rohs-compliant 165-pin bga 167 c mp 512k x 36 gs8182q36gd-133 sigmaquad-ii sram rohs-compliant 165-pin bga 133 c mp 512k x 36 gs8182q36gd-200i sigmaquad-ii sram rohs-compliant 165-pin bga 200 i mp 512k x 36 gs8182q36gd-167i sigmaquad-ii sram rohs-compliant 165-pin bga 167 i mp 512k x 36 gs8182q36gd-133i sigmaquad-ii sram rohs-compliant 165-pin bga 133 i mp notes: 1. customers requiring delivery in tape and reel should add the character ?t? to the end of the part number . example: gs818x36d- 200t . 2. t a = c = commercial temperature range. t a = i = industrial temperature range. 3. mp = mass production. gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 29/30 ? 2003, gsi technology n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t
sigmaquad-ii revision history file name format/content description of changes 8182qxx_r1 creation of datasheet 8182qxx_r1; 8182qxx_r1_01 content ? updated ac specs 8182qxx_r1_01; 8182qxx_r1_02 content/format ? removed x36 configuration ? updated format ? removed 250 mhz speed bin 8182qxx_r1_02; 8182qxx_r1_03 content/format ? removed x36 configuration ? updated format ? removed erroneous speed bins ? updated read description 8182qxx_r1_03; 8182qxx_r1_04 content ? added pb-free information ? added clock to /clock delay timing to ac characteristics tab l e ? updated max spec for tkhkh ? added storage under bias information ? added operating currents specs 8182qxx_r1_04; 8182qxx_r1_05 content ? updated document for mp qualification ? removed 250 mhz speed bin ? added 200 mhz for x36 ? (rev1.05c: added missing x36 pinout) gs8182q18/36d-200/167/133 specifications cited are subject to change without notice . for latest documentation see http://www.gsitechnology.com. rev: 1.05c 2/2007 30/30 ? 2003, gsi technology n ot r e c omm e n d e d f or ne w d e s i g n ?d i sc on t i n u e d p r o d uc t

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